library ieee;
use ieee.std_logic_1164.all;
use work.mis_componentes.all;


entity mplex8x1_2 is	

port(a,b,c,d,e,f,g,h:in std_logic;
	s :in std_logic_vector(2 downto 0);
	q:out std_logic);
end mplex8x1_2;


architecture bhv of mplex8x1_2 is
signal temp:std_logic_vector(1 downto 0);
begin


U1: mplex4x1 PORT MAP(a=>a,b=>b,c=>c,d=>d,s=>(s(1)&s(0)),f=>temp(0));
U2: mplex4x1 PORT MAP(a=>e,b=>f,c=>g,d=>h,s=>(s(0)&s(1)),f=>temp(1));
U3: mplex2x1 PORT MAP(a=>temp(0),b=>temp(1),s=>s(2),f=>q);



end bhv;